Design and Implementation of Soft core Processor on FPGA based on Avalon Bus and SOPC Technology

Nios II is a soft Processor that can be incorporated in system implemented on a FPGA device by using Avalon Interface & SOPC technology. It allows easy interfacing of new peripheral blocks to existing software. The FPGA has the capability of parallel processing and hardware modification. It offers the possibility of microprocessor implementations, which can be programmed in assembly or C. The NIOS II is a versatile embedded processor family that presents high performance and has been created for FPGA. The NIOS II Processor propitiates flexibility in the implementation of the processor system such an as: Choose the exact set of CPUs, peripherals, and interfaces needed for the application; increase performance without changing board design, accelerating only functions that require it; eliminate the risk of processor obsolescence; lower overall cost, complexity, and power consumption combining many functions into one chip. In this paper Nios II Soft processor provided by ALTERA is Implemented On Cyclon II FPGA using Avalon bus & SOPC Technology, where Avalon interfaces simplify system design by allowing designer to easily connect components in an Altera FPGA. SOPC Builder enables designer to define and generate a complete system-on-a-programmable-chip (SOPC) in much less time than using traditional, manual integration methods. The Nios II family of embedded processors consists of three processor cores that implement a common instruction set architecture, each optimized for specific performance point and all are supported by same software tool chain.