Asynchronous sigma delta modulators for data conversion

The research carried out in this thesis focuses on introducing solutions to solve issues existed in asynchronous sigma delta modulators including complex decoding scheme, lacking of noise shaping and effects of limit cycle components. These issues significantly limit the implementation of ASDMs in data conversion. The first innovation in this work is the introduction of a novel decoding circuit to digitise the output signal of the asynchronous sigma delta modulator. Compared with the conventional decoding schemes, the proposed one does not limit the input dynamic range of ASDMs, and can obtain a high resolution without a fast sample clock. The proposed decoding circuit operates asynchronously and can measure the duty cycle of the modulated square wave without measuring its instantaneous period. The second innovation of this work is the introduction of a novel architecture of the asynchronous sigma delta modulator with noise shaping without an additional loop filter. Moreover, the proposed modulator requires only a single-bit digital-to-time converter in the feedback loop even for a multi-bit quantiser. The quantiser in the modulator is realized by an eight-phase poly-phase sampler in order to reduce the requirement of the sample clock. Simulation demonstrate that the SNDR of the proposed modulator can be improved by 20dB. The final innovation of this work is the introduction of frequency compensation to the asynchronous sigma delta modulator. In this proposed modulator, the limit cycle frequency is controlled by the delay time of a novel high linear performance delay line, which is operated in current mode. The compensation is realized by adjusting the equivalent delay time for different input voltage values. The proposed one can double the signal bandwidth with the same limit cycle frequency.

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