Estimating BIST Resources in High-level Synthesis
暂无分享,去创建一个
[1] Haidar Harmanani,et al. An improved method for RTL synthesis with testability tradeoffs , 1993, ICCAD.
[2] T. Kailath,et al. VLSI and Modern Signal Processing , 1984 .
[3] LaNae J. Avra,et al. ALLOCATION AND ASSIGNMENT IN HIGH-LEVEL SYNTHESIS FOR SELF-TESTABLE DATA PATHS , 1991, 1991, Proceedings. International Test Conference.
[4] Nikil D. Dutt,et al. Comprehensive Lower Bound Estimation From Behavioral Descriptions , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[5] Yuan Hu,et al. Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.
[6] Robert A. Walker,et al. Computing lower bounds on functional units before scheduling , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.
[7] Daniel P. Siewiorek,et al. Automated Synthesis of Data Paths in Digital Systems , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Parimal Pal Chaudhuri,et al. Design of Testable VLSI Circuits with Minumum Area Overhead , 1989, IEEE Trans. Computers.
[9] Rajiv Jain,et al. Area-time model for synthesis of non-pipelined designs , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[10] Alice C. Parker,et al. Predicting system-level area and delay for pipelined and nonpipelined designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Alok Sharma,et al. Estimating Architectural Resources and Performance for High-Level Synthesis Applications , 1993, 30th ACM/IEEE Design Automation Conference.
[12] Alice C. Parker,et al. Data path tradeoffs using MABAL , 1991, DAC '90.
[13] Minjoong Rim,et al. Estimating lower-bound performance of schedules using a relaxation technique , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[14] Melvin A. Breuer,et al. Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead , 1995, 32nd Design Automation Conference.
[15] K. Kucukcakar,et al. Data path tradeoffs using MABAL , 1990, 27th ACM/IEEE Design Automation Conference.
[16] Pierre G. Paulin,et al. Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] Alex Orailoglu,et al. SYNCBIST: SYNthesis for concurrent built-in self-testability , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[18] Magdy Abadir,et al. A Knowledge-Based System for Designing Testable VLSI Chips , 1985, IEEE Design & Test of Computers.