Performance analysis of flagged prefix adders with logical effort

This paper studies an adder technique that performs three input addition utilizing parallel prefix adders. The adder architectures are called three-input flagged prefix adders (TIFPA) due to the utilization of a new set of intermediate outputs called flag bits to obtain the desired result. One of the advantages of this technique is the elimination of dedicated adder units to perform three-input addition. This adder can find its use in applications such as multiplication or multi-media units. This paper examines the effect on the performance of the adder when the operand size is expanded from 16 bits to 32 and 64 bits. Furthermore, a logical effort analysis has also been performed on the TIFPA to confirm the simulation and analytical results. The performance of this adder design has been compared to that of carry save adders (CSA) to understand the performance gain of the proposed technique. The comparison has been made with respect to the simulation results and also on the basis of logical effort.

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