论文信息 - A fast method for timing verification that uses the conditions that cause changes in the output values of gates

A fast method for timing verification that uses the conditions that cause changes in the output values of gates

This paper discusses a fast method for timing verification which uses the conditions that cause changes in the output value of gates in a combinational logic circuit. The methods proposed previously derive the conditions that make a circuit behave correctly and incorrectly, but the new method in this paper derives only the latter. The new method also efficiently decides whether the derived condition is satisfied or not. Scripta Technica, Syst Comp Jpn, 32(1): 3844, 2001

Yuji Sugiyama | Atsushi Ohnishi

[1] Nagisa Ishiura,et al. Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits , 1989, 26th ACM/IEEE Design Automation Conference.

[2] Tomohiro Yoneda,et al. A fast timing verification method based on the independence of units , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.