Reconfigurable Digital Front-End Hardware for Wireless Base-Station Transmitters: Analysis, Design and FPGA Implementation

A versatile digital front-end architecture is designed and implemented on field-programmable gate array (FPGA) technology. The architecture includes the digital up-conversion, and peak-to-average power ratio (PAPR) reduction blocks that are applicable to down-link data paths in multi-band wireless base stations such as WCDMA or Wimax systems. Transmitter linearity requirements are addressed and tradeoff analysis for design and optimization of the PAPR reduction algorithm within the context of the error vector magnitude and adjacent channel leakage ratio quality metrics are studied. Statistical characteristics of the clipping noise are analyzed and a novel method for clipping the multi-band signal under the phase invariant constraint is proposed. Our study also includes mapping of the signal processing algorithms onto Xilinx Virtex-4trade FPGA device and addresses the resource utilization and efficient hardware implementation of the above signal processing blocks. Performance assessments and hardware validation of the proposed architecture are also addressed.

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