Constraint-Driven Test Scheduling for NoC-Based Systems

On-chip integrated network, the so-called network-on-chip (NoC), is becoming a promising communication paradigm for the next-generation embedded core-based system chips. The reuse of the on-chip network as test access mechanism has been recently proposed to handle the growing complexity of testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test-scheduling methods are required to deliver feasible test time while meeting all the constraints. In this paper, the authors propose a comprehensive approach to test scheduling in NoC-based systems. The proposed scheduling algorithm is based on the use of dedicated routing path that is suitable for nonpreemptive test. The algorithm is improved by incorporating both preemptive and nonpreemptive tests. In addition, BIST, precedence, and power constraints were taken into consideration. Experimental results for the ITC'02 system-on-chip benchmarks show that the nonpreemptive scheduling based on dedicated path can efficiently reduce test application time compared to previous work, and the improved method provides a practical solution to the real-world NoC-based-system testing with both preemptive and nonpreemptive cores. It is also shown that various constraints can be incorporated to deliver a comprehensive test solution

[1]  Sabih H. Gerez,et al.  Algorithms for VLSI design automation , 1998 .

[2]  A. Ivanov,et al.  A packet switching communication-based test access mechanism for system chips , 2001, IEEE European Test Workshop, 2001..

[3]  Kees G. W. Goossens,et al.  Bringing communication networks on a chip: test and verification implications , 2003, IEEE Commun. Mag..

[4]  Chouki Aktouf,et al.  A complete strategy for testing an on-chip multiprocessor architecture , 2002, IEEE Design & Test of Computers.

[5]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[6]  Irith Pomeranz,et al.  SOC test scheduling using simulated annealing , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[7]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[8]  Erik Jan Marinissen,et al.  Effective and efficient test architecture design for SOCs , 2002, Proceedings. International Test Conference.

[9]  Mounir Benabdenbi,et al.  CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing , 2002, J. Electron. Test..

[10]  Cheng-Wen Wu,et al.  A Graph-Based Approach to Power-Constrained SOC Test Scheduling , 2004, J. Electron. Test..

[11]  Chunsheng Liu,et al.  Thermal-aware test scheduling and hot spot temperature minimization for core-based systems , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[12]  Luigi Carro,et al.  A study on communication issues for systems-on-chip , 2002, Proceedings. 15th Symposium on Integrated Circuits and Systems Design.

[13]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[15]  Krishnendu Chakrabarty,et al.  System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Vittorio Zaccaria,et al.  System level power modeling and simulation of high-end industrial network-on-chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[17]  Dipanwita Roy Chowdhury,et al.  An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch , 2002, J. Electron. Test..

[18]  Sandeep Koranne,et al.  On the use of k-tuples for SoC test schedule representation , 2002, Proceedings. International Test Conference.

[19]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[20]  Krishnendu Chakrabarty,et al.  Test scheduling for core-based systems using mixed-integer linearprogramming , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Nilanjan Mukherjee,et al.  Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm , 2002, Proceedings. International Test Conference.

[22]  Luigi Carro,et al.  Reusing an on-chip network for the test of core-based systems , 2004, TODE.

[23]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[24]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[25]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[26]  André Ivanov,et al.  Indirect test architecture for SoC testing , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Luigi Carro,et al.  The impact of NoC reuse on the testing of core-based systems , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[28]  Erik Jan Marinissen,et al.  Cluster-based test architecture design for system-on-chip , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[29]  Sandeep Koranne.  Formulation of SOC Test Scheduling as a Network Transportation Problem , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Luigi Carro,et al.  Test planning and design space exploration in a core-based environment , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[31]  Peter Harrod,et al.  Testing reusable IP-a case study , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[32]  Krishnendu Chakrabarty,et al.  Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).