A 10-bit 60 Msps flash ADC

A 60-mega-sample/sec 10-bit flash analog-to-digital converter (ADC) that uses interpolation from 512 preamplifiers to derive 1023 parallel latches is described. The ADC was designed in a bipolar process offering three layers of metal interconnect and an effective emitter area of 0.8 mu m/sup 2/. Typical currents are 100 mu A for 300-ps gate delays. Overall design concerns are discussed. The advantages of the architecture are analyzed, focusing on the interpolation technique and the comparator design.<<ETX>>