A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology

A 16*16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has been optimized to balance the delays in different sections of the chip. A typical multiplication time of 6.75 ns at 3.3 V power supply has been measured, and better results are expected from a process optimized for 0.5 mu m devices. >

[1]  J. Greene,et al.  A CMOS 32b Wallace tree multiplier-accumulator , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  A. Lopez,et al.  A dense gate matrix layout style for MOS LSI , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Ramautar Sharma.  Area-time efficient arithmetic elements for VLSI systems , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[4]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[5]  R. L. Field,et al.  A symmetric submicron CMOS technology , 1986, 1986 International Electron Devices Meeting.

[6]  M. Suzuki,et al.  Prospects of SST technology for high speed LSI , 1985, 1985 International Electron Devices Meeting.