A Single Flux Quantum Cryogenic Random Access Memory

We report on the design of a superconductive Cryogenic Random Access Memory (CRAM). The 16-Kb RAM consists of four 4-Kb sub-arrays (blocks). It will have a 400 ps access time (latency) and a 100 ps cycle time (throughput). The input data and address are distributed using a high-speed RSFQ pipelined demultiplexer. The output data is collected with an RSFQ pipelined multiplexer. The entire 16-Kb RAM chip will dissipate 2.4 mW. We also discuss the projection for this design, using a future sub-micron fabrication process to achieve a 1-Mb capacity with a 40 ps throughput, required for HTMT (PetaFLOPS computing) project.