A Sub-wavelength SoC Design Flow to Improve Yield

Various types of layout hot spots are found in sub-wavelength SoC designs. This paper describes the root causes of these failure mechanisms that will lead to random, systematic and parametric failures. It offers a number of suggestions to mitigate these layout hot spot issues, including hot spot tradeoff analysis and automatic hot spot repair using physical layout optimization. It highlights the trends in design flow evolution from 0.25μm technology node to present day deep subwavelength technologies, including the need for CAA and litho simulation in addition to traditional design rule checks. Sub-wavelength hot spots impact both cell level (critical layers) layouts as well as full chip layouts. Layout hot spots at critical layers must be addressed at the cell library level and interconnect level hot spots need to be addressed at the full chip level.