Feasible regions quantify the probabilistic configuration power of arrays with multiple fault types

The bulk of results for the performance of configuration architectures treat the case of failed processor, but neglect switches that are stuck open or closed. By contrast, the present work characterizes this multivariate problem in the presence of either independent and identically distributed (iid) or clustered faults. Suppose that the designer wishes to assure, with high probability, a fault-free s/spl times/t array. If local sparing is used then, as we report, the resulting area is (i) /spl Theta/(st log st) in the presence of faulty elements or faulty elements and switches stuck open; (ii) /spl Theta/(st log/sup 2/ st) in the presence of faulty elements and switches stuck closed; (iii) /spl Theta/([st]/sup 2/ log st) in the presence of faulty elements and switches that may be either stuck open or stuck closed. We also furnish bounds on maximum wirelength and an optimal configuration algorithm.

[1]  L. LaForge,et al.  Extremally fault tolerant arrays , 1989, [1989] Proceedings International Conference on Wafer Scale Integration.

[2]  M. B. Ketchen.  Point defect yield model for wafer scale integration , 1985, IEEE Circuits and Devices Magazine.

[3]  Israel Koren,et al.  The impact of floorplanning on the yield of fault-tolerant ICs , 1995, Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI).

[4]  E. Artin,et al.  The Gamma Function , 1964 .

[5]  Jeffrey D Ullma.  Computational Aspects of VLSI , 1984 .

[6]  Frank Thomson Leighton,et al.  Wafer-Scale Integration of Systolic Arrays , 1985, IEEE Trans. Computers.

[7]  Israel Koren,et al.  A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits , 1993, IEEE Trans. Computers.

[8]  Glenn H. Chapman,et al.  Test vehicle for a wafer-scale thermal pixel scene simulator , 1994 .

[9]  L. E. LaForge,et al.  What designers of wafer scale systems should know about local sparing , 1994, Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI).

[10]  Sy-yen Kuo,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987, IEEE Design & Test of Computers.

[11]  D.K. Pradhan,et al.  Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems , 1986, Proceedings of the IEEE.

[12]  Janusz Rajski,et al.  Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays , 1989 .

[13]  Laurence E. Laforge.  Fault tolerant arrays , 1992 .

[14]  Vinod K. Agarwal,et al.  A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing , 1995, IEEE Trans. Parallel Distributed Syst..

[15]  B. T. Murphy,et al.  Cost-size optima of monolithic integrated circuits , 1964 .