A 10-bit 70 MS/s CMOS D/A converter

A 10-bit 70-MS/s D/A (digital-to-analog) converter fabricated in a 1-mm CMOS process is described. A linearity within p0.5 LSB has been realized by a new switching sequence that is based on hierarchical error cancellation and suppresses both graded and symmetrical errors distributed in outputs of current sources. A layout technique for suppressing the influence of transistors implanted in tilt angles on linearity is also discussed

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