A Novel Adiabatic Technique for Energy Efficient Logic Circuits Design

As we are moving ahead in technology, the sizes of various gadgets and devices is reducing which means we need to size down the CMOS logic cells. Adiabatic logic circuits are one of the most efficient technologies that are being used today to minimise power consumption. Different adiabatic logic families such as ECRL, 2N-2N2P and PFAL are investigated in this paper. All simulations have been carried out with W/L ratio of all the circuits kept same for fair comparison of results. HSPICE has been used at 65nm technology with supply voltage of 1V at 100MHz frequency, finally plotting of average power dissipation characteristics have been done with the help of a graph and different logic families' comparisons have been done.

[1]  Haranath Kar,et al.  Multi-threshold CMOS design for low power digital circuits , 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

[2]  V. S. Kanchana Bhaaskaran,et al.  Energy recovery performance of quasi-adiabatic circuits using lower technology nodes , 2011, India International Conference on Power Electronics 2010 (IICPE2010).

[3]  Vandana Niranjan,et al.  PFAL based power efficient mux based decoder , 2015, International Conference on Computing, Communication & Automation.

[4]  Takashi Ishikawa,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[5]  Eby G. Friedman,et al.  Multi-voltage CMOS Circuit Design , 2006 .

[6]  Vivek De,et al.  A new technique for standby leakage reduction in high-performance circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[7]  Manoj Sharma,et al.  Design of basic gates using ECRL and PFAL , 2013, 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

[8]  L. Reyneri,et al.  Positive feedback in adiabatic logic , 1996 .

[9]  Ajay Kumar Dadoria,et al.  A novel efficient adiabatic logic design for ultra low power , 2016, 2016 International Conference on ICT in Business Industry & Government (ICTBIG).

[10]  R.W. Brodersen,et al.  A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.

[11]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[12]  Eby G. Friedman,et al.  Domino logic with variable threshold voltage keeper , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Massoud Pedram,et al.  Charge recycling in MTCMOS circuits: concept and analysis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[14]  Ajay Kumar Dadoria,et al.  Ultra Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL Logic , 2017 .

[15]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[16]  Sanjeev Kumar.  Implementation of low power CMOS design using Adiabatic Improved Efficient Charge Recovery Logic , 2014 .

[17]  Deog-Kyoon Jeong,et al.  An efficient charge recovery logic circuit , 1996, IEEE J. Solid State Circuits.

[18]  Ankita Mishra,et al.  Low power cmos cell structures based on adiabatic switching , 2016, 2016 International Conference on Communication and Electronics Systems (ICCES).

[19]  Vijaya Bhadauria,et al.  Low power adiabatic logic using DCPAL block , 2014, 2014 Students Conference on Engineering and Systems.

[21]  Jiajing Wang,et al.  Sub-threshold circuit design with shrinking CMOS devices , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[22]  Aruna Rani,et al.  Adiabatic Split Level Charge Recovery Logic Circuit , 2013 .

[23]  Robert F. Pierret,et al.  Semiconductor device fundamentals , 1996 .

[24]  John S. Denker,et al.  2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits , 1995, ISLPED '95.