A New Current-Mode Incremental Signaling Scheme With Applications to Gb/s Parallel Links

A new current-mode incremental signaling (CMIS) scheme and a new fully differential current-integrating receiver for high-speed parallel links are presented. The proposed signaling scheme requires only N+1 physical paths for N parallel bits. It possesses the intrinsic advantages of current-mode signaling including high data rates, large signal swing, low switching noise injection, and superior signal integrity. The current-integrating receiver consisting of a transimpedance front-end, an integrator, and a sense amplifier with active inductor shunt peaking offers the key advantages of a low and tunable input impedance for channel termination, large bandwidth, and effective suppression of transient noise coupled to the channels. To assess the effectiveness of the proposed signaling scheme and the current-integrating receiver, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10-cm microstrip lines with FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13-mum 1.2-V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3V device models. Simulation results demonstrate that the proposed CMIS scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5GB/s

[1]  Anthony Chan Carusone,et al.  Differential signaling with a reduced number of signal paths , 2001 .

[2]  M. Horowitz,et al.  A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation , 2000, IEEE Journal of Solid-State Circuits.

[3]  Tao Wang,et al.  A new current-mode incremental signaling scheme with applications to Gb/s parallel links , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[4]  JEAN JIANG,et al.  A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links , 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).

[5]  Amer Hani Atrash.  Data Bus Deskewing Systems in Digital CMOS Technology , 2004 .

[6]  T. J. Gabara,et al.  Digitally adjustable resistors in CMOS for high-performance applications , 1992 .

[7]  Cecilia Metra,et al.  Fast and low-cost clock deskew buffer , 2004 .

[8]  Daniel P. Foty,et al.  MOSFET Modeling With SPICE: Principles and Practice , 1996 .

[9]  Tetsuo Endoh,et al.  0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation , 2001, IEEE J. Solid State Circuits.

[10]  B.W. Garlepp,et al.  1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[11]  Takashi Sato,et al.  A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM , 1999 .

[12]  Brian Butka,et al.  A technique to deskew differential PCB traces , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[13]  D.A. Johns,et al.  A CMOS 10-gb/s power-efficient 4-PAM transmitter , 2004, IEEE Journal of Solid-State Circuits.

[14]  Fei Yuan,et al.  CMOS Current-Mode Circuits for Data Communications (Analog Circuits and Signal Processing) , 2006 .

[15]  W.J. Dally,et al.  Low-power area-efficient high-speed I/O circuit techniques , 2000, IEEE Journal of Solid-State Circuits.

[16]  A. Boni,et al.  LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS , 2001 .

[17]  Michael P. Flynn,et al.  A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS , 2001 .

[18]  Lei Wang,et al.  An energy-efficient skew compensation technique for high-speed skew-sensitive signaling , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[19]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[20]  Stephen P. Boyd,et al.  Bandwidth extension in CMOS with optimized on-chip inductors , 2000, IEEE Journal of Solid-State Circuits.

[21]  Mark Horowitz,et al.  A 700-Mb/s/pin CMOS signaling interface using current integrating receivers , 1997 .