Modelling of the Signal Delay Induced by PCB Interconnect SISO Structure
暂无分享,去创建一个
[1] D. Deschacht,et al. Impact of inductance and routing orientation on timing performances of coupled interconnect lines , 2010, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.
[2] Uri C. Weiser,et al. Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.
[3] Andrew B. Kahng,et al. An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Moustafa A. Sayed,et al. Interconnect Synthesis in High Speed Digital VLSI Routing , 2009 .
[5] Blaise Ravelo,et al. A New Technique of Interconnect Effects Equalization by Using Negative Group Delay Active Circuits , 2010 .
[6] Yehea I. Ismail,et al. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[7] W. C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .
[8] Luca P. Carloni,et al. Accurate Predictive Interconnect Modeling for System-Level Design , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[9] Eby G. Friedman,et al. Repeater design to reduce delay and power in resistive interconnect , 1998 .
[10] James D. Meindl,et al. Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions , 2000 .
[11] J.S. Kilby,et al. Invention of the integrated circuit , 1976, IEEE Transactions on Electron Devices.
[12] Blaise Ravelo,et al. Fast estimation of RL-loaded microelectronic interconnections delay for the signal integrity prediction , 2012 .
[13] L.P.P.P. van Ginneken,et al. Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .
[14] B. Ravelo,et al. Experimental Validations of a Simple PCB Interconnect Model for High-Rate Signal Integrity , 2012, IEEE Transactions on Electromagnetic Compatibility.
[15] Jason Cong,et al. LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] W. Bandurski,et al. Effect of inductance on interconnect propagation delay in VLSI circuits , 2004, Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects.
[17] Gerard V. Kopcsay,et al. High-Speed Signal Propagation on Lossy Transmission Lines , 1990, IBM J. Res. Dev..
[18] Jamil Kawa,et al. Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[19] Víctor H. Champac,et al. Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[20] A. Orlandi,et al. Signal and Power Integrity Performances of Striplines in Presence of 2D EBG planes , 2008, 2008 12th IEEE Workshop on Signal Propagation on Interconnects.
[21] Blaise Ravelo,et al. Demonstration of negative signal delay with short-duration transient pulse , 2011 .
[22] R. Achar. Advanced modeling and simulation methodologies for signal integrity analysis , 2008, 2008 International Conference on Recent Advances in Microwave Theory and Applications.
[23] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[24] R. K. Sharma,et al. VLSI interconnects and their testing: prospects and challenges ahead , 2011 .
[25] Yu Cao,et al. Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[26] Jun-Fa Mao,et al. Global interconnect width and spacing optimization for latency, bandwidth and power dissipation , 2005 .
[27] Gaston H. Gonnet,et al. On the LambertW function , 1996, Adv. Comput. Math..
[28] Blaise Ravelo,et al. Investigation on Microwave Negative Group Delay Circuit , 2011 .
[29] Paul Ampadu,et al. Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[30] Yehea I. Ismail,et al. Equivalent Elmore delay for RLC trees , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[31] Walter Anheier,et al. Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays , 2009, 2009 IEEE Workshop on Signal Propagation on Interconnects.
[32] Blaise Ravelo,et al. Cancellation of Delays in the High-Rate Interconnects with UWB NGD Active Cells , 2011 .
[33] Pavan Kumar Hanumolu,et al. EQUALIZERS FOR HIGH-SPEED SERIAL LINKS , 2005 .
[34] Gordon E. Moore,et al. Progress in digital integrated electronics , 1975 .
[35] Blaise Ravelo,et al. TRANSIENT RESPONSE CHARACTERIZATION OF THE HIGH-SPEED INTERCONNECTION RLCG-MODEL FOR THE SIGNAL INTEGRITY ANALYSIS , 2011 .
[36] Markku Rouvala,et al. Multi-gigabit serial link emissions and mobile terminal antenna interference , 2009, 2009 IEEE Workshop on Signal Propagation on Interconnects.
[37] B. Raveloa. Delay modeling of high-speed distributed interconnect for the signal integrity prediction , 2012 .