On the impact of mechanical stress on gate oxide trapping

The electrical performance and reliability of MOSFETs and charge-trap flash memories are influenced by the traps in the gate dielectric. Trap properties depend on the atomic structure of the dielectric and are thus expected to be affected by mechanical stress, which modifies the bonds between atoms. Consequently, the mechanical stress, either engineered or created as a side effect of fabrication, needs to be considered in order to improve the device performance and reliability. This work demonstrates a systematic and controlled experimental study of the trapping process in individual gate oxide defects under externally applied mechanical stress. The significant and reversible impact of the mechanical stress on the trapping behavior is demonstrated and a theory to explain the observations is proposed.

[1]  Miss A.O. Penney (b) , 1974, The New Yale Book of Quotations.

[2]  Tiit Kärner,et al.  Defect structure relaxation process in the Si–SiO2 system , 2000 .

[3]  V. Senez,et al.  Investigations of stress sensitivity of 0.12 CMOS technology using process modeling , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[4]  A. ADoefaa,et al.  ? ? ? ? f ? ? ? ? ? , 2003 .

[5]  M. Jurczak,et al.  Exploring the limits of stress-enhanced hole mobility , 2005, IEEE Electron Device Letters.

[6]  T. Grasser,et al.  The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability , 2010, 2010 IEEE International Reliability Physics Symposium.

[7]  M. Koyanagi 3D integration technology and reliability , 2011, 2011 International Reliability Physics Symposium.

[8]  G. Beyer,et al.  Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology , 2012, 2012 International Electron Devices Meeting.

[9]  K. J. Kuhn,et al.  Considerations for Ultimate CMOS Scaling , 2012, IEEE Transactions on Electron Devices.

[10]  Philippe Roussel,et al.  Toward a streamlined projection of small device bias temperature instability lifetime distributions , 2013 .

[11]  A. Shluger,et al.  Nature of intrinsic and extrinsic electron trapping in SiO2 , 2014 .

[12]  T. Grasser Bias Temperature Instability for Devices and Circuits , 2014 .

[13]  I. De Wolf,et al.  Extraction of elastic modulus of porous ultra-thin low-k films by two-dimensional finite-element simulations of nanoindentation , 2016 .

[14]  Tibor Grasser,et al.  Identification of oxide defects in semiconductor devices: A systematic approach linking DFT to rate equations and experimental evidence , 2018, Microelectron. Reliab..

[15]  Francky Catthoor,et al.  A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability , 2018, Microelectron. Reliab..

[16]  E. Beyne,et al.  Characterization of Impact of Vertical Stress on FinFETs , 2019, 2019 22nd European Microelectronics and Packaging Conference & Exhibition (EMPC).

[17]  I. De Wolf,et al.  Impact of Mechanical Stress on the Electrical Performance of 3D NAND , 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

[18]  Tsuyoshi Murata,et al.  {m , 1934, ACML.