A new and flexible scheme for hot-electron programming of nonvolatile memory cells

A new hot electron writing scheme for flash EEPROMs is proposed that combines a positive source to bulk voltage and a ramped voltage on the control gate. The scheme exploits the equilibrium between hot electron injection and displacement current at the floating gate electrode in order to achieve a transient regime where the drain current of the cell is virtually constant. The new method allows one to accurately control the threshold voltage and the programming drain current that is essentially determined by the slope of the control gate ramp and can thus be traded off with programming time over a wide range of values. The main features of the new scheme are experimentally demonstrated on up-to-date 0.6 /spl mu/m stacked gate flash EEPROM devices.

[1]  B. Eitan,et al.  Multilevel flash cells and their trade-offs , 1996, International Electron Devices Meeting. Technical Digest.

[2]  R. Bez,et al.  Temperature dependence of gate and substrate currents in the CHE crossover regime , 1995, IEEE Electron Device Letters.

[3]  S. Muramatsu,et al.  The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[4]  B. Bandyopadhyay,et al.  Substrate-current-induced hot electron (SCIHE) injection: a new convergence scheme for flash memory , 1995, Proceedings of International Electron Devices Meeting.

[5]  L. Ravazzi,et al.  A novel method for the experimental determination of the coupling ratios in submicron EPROM and flash EEPROM cells , 1990, International Technical Digest on Electron Devices.

[6]  Shojiro Asai,et al.  New hot-carrier injection and device degradation in submicron MOSFETs , 1983 .

[7]  F. Masuoka Technology trend of flash-EEPROM-Can flash-EEPROM overcome DRAM? , 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

[8]  Ching-Yuan Wu,et al.  Physical model for characterizing and simulating a FLOTOX EEPROM device , 1992 .

[9]  A. Frommer,et al.  EEPROM/flash sub 3.0 V drain-source bias hot carrier writing , 1995, Proceedings of International Electron Devices Meeting.

[10]  E. Takeda,et al.  Hot-carrier effects in submicrometre MOS VLSIs , 1984 .

[11]  Chee Yee Kwok,et al.  A study of trapezoidal programming waveform for the FLOTOX EEPROM , 1993 .

[12]  D. Cantarelli,et al.  Experimental transient analysis of the tunnel current in EEPROM cells , 1990 .

[13]  B. Bandyopadhyay,et al.  A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection , 1995, IEEE Electron Device Letters.

[14]  Min-Hwa Chi,et al.  Multi-level flash/EPROM memories: new self-convergent programming methods for low-voltage applications , 1995, Proceedings of International Electron Devices Meeting.

[15]  Kuniyoshi Yoshikawa,et al.  Process and device technologies for 16 Mbit EPROMs with large-tilt-angle implanted p-pocket cell , 1990, International Technical Digest on Electron Devices.

[16]  T. Iizuka,et al.  Determination of threshold energy for hot electron interface state generation , 1996, International Electron Devices Meeting. Technical Digest.

[17]  Min-Hwa Chi,et al.  A new erase VT distribution model for reliability design in high density flash EEPROM , 1995, 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.

[18]  K. Yoshikawa,et al.  Comparison of current flash EEPROM erasing methods: stability and how to control , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[19]  Y. Nissan-Cohen,et al.  A novel floating-gate method for measurement of ultra-low hole and electron gate currents in MOS transistors , 1986, IEEE Electron Device Letters.