Low-Overhead SEU-Tolerant Latches

Two latches, named SEUT-A and SEUT-B respectively, designed to tolerate radiation-induced Single Event Upset (SEU) are presented. SEU immunity is achieved by storing data on different nodes and through the recovery mechanism of the circuits. Neither of the designs needs transistor sizing to be functional and SEU-tolerant, so it can be implemented by small devices. The proposed structures are implemented and simulated using a standard 0.18 mum logic process model. Simulation results show that both of the proposed latches are less power- consumptive than that based on Dual Interlocked Cell (DICE). Compared to unhardened latch, SEUT-A uses only 11% more transistors and is 6% slower, whereas SEUT-B uses 56% more transistors but is 43% faster.