Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference

In this article, we propose an efficient correlated Bayesian inference (CBI) method to estimate the system-level failure rates for large-scale circuit systems over multiple process corners. The key idea is to encode the correlations of circuit performances among the different corners into the prior distributions of several carefully defined failure events. The hyper-parameters of these distributions can be learned from a few simulation samples via Bayesian inference and, next, the system-level failure rates over different corners can be simultaneously estimated by taking into account these prior distributions. An iteratively constrained inference method is further developed to guarantee the numerical stability of the proposed method and legalize all estimated failure rates. The numerical experiments demonstrate that compared to the state-of-the-art algorithm, the proposed method can achieve around $10\times $ runtime reduction without surrendering any accuracy.

[1]  I. Miller Probability, Random Variables, and Stochastic Processes , 1966 .

[2]  Xin Li,et al.  Correlated Bayesian model fusion: Efficient performance modeling of large-scale tunable analog/RF integrated circuits , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[3]  Xuan Zeng,et al.  C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Xuan Zeng,et al.  Correlated rare failure analysis via Asymptotic Probability Evaluation , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  Rob A. Rutenbar,et al.  Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS , 2008, Proceedings of the IEEE.

[6]  Xin Li,et al.  Fast statistical analysis of rare circuit failure events via Bayesian scaled-sigma sampling for high-dimensional variation space , 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

[7]  Witold Pedrycz,et al.  Minimizing the number of process corner simulations during design verification , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Xin Li,et al.  Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation space , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Radford M. Neal Pattern Recognition and Machine Learning , 2007, Technometrics.

[10]  Thomas M. Cover,et al.  Elements of Information Theory , 2005 .

[11]  Rajiv V. Joshi,et al.  Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[12]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[13]  Aarnout Brombacher,et al.  Probability... , 2009, Qual. Reliab. Eng. Int..

[14]  Rob A. Rutenbar,et al.  Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Xin Li,et al.  Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[16]  Brian Neelon,et al.  Bayesian Isotonic Regression and Trend Analysis , 2004, Biometrics.

[17]  Hiroyuki Ochi,et al.  Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[18]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.