Sleepy Keeper Approach for Power Performance Tuning in VLSI Design

There are several techniques that reduce leakage power in efficient way but the disadvantage of each technique limits the application of each technique. In this paper sleepy keeper approach is introduced to reduce the power dissipation of the circuit in idle state when its logic is not needed. The sleepy keeper approach uses traditional sleep transistors and two additional transistors which are driven by already calculated gate output. This saves the state during sleep mode. Multi threshold transistors are used in order to reduce subthreshold leakage power and also to increase the switching speed of the circuit.

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