Low-power and robust six-FinFET memory cell using selective gate-drain/source overlap engineering

A new FinFET memory circuit technique based on gate-drain/source overlap engineering is proposed in this paper. The read stability of the proposed SRAM circuit is enhanced by 53% and the leakage power is reduced by 48% as compared to a minimum sized low-threshold-voltage FinFET SRAM cell in a 32nm FinFET technology. Furthermore, the layout area of the proposed SRAM circuit is reduced by 17% as compared to a FinFET SRAM circuit with longer-channel access transistors. The proposed technique based on gate-drain/source overlap engineering is easier to be implemented with fewer processing steps as compared to the previously published data stability enhancement techniques based on independent-gate bias and gate work-function engineering in FinFET memory circuits.

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