6.1 memory and system architecture for 400Gb/s networking and beyond
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Networking relies on fast line card packet rates that are directly proportional to and limited by the Random Transaction Rate (RTR) of the memory system. Networking line cards to date are ≤200Gb/s and were able to use memories optimized for latency (SRAM) and bandwidth (SDRAM) designed for computing systems. Next generation line cards are ≥400Gb/s and the memory system for these line cards need to be explicitly architected and designed for delivering the required high RTR.
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[2] Douglas Yu. Innovative wafer-based interconnect enabling system integration and semiconductor paradigm shifts , 2013, 2013 IEEE International Interconnect Technology Conference - IITC.