A VLSI architecture for a dedicated back-propagation simulator

Summary form only given, as follows. A VLSI architecture for a fully dedicated backpropagation algorithm processor is discussed. This processor contains 4 multipliers and 4 ALU's (arithmetic and logic units) which can work in parallel. The connections of these functional units change according to the current stage of the backpropagation algorithm. The data format is 24-bit floating point (allowing for integers up to 18E6) with an estimated performance of 20 million connection updates per second (MCUPS) at 40 MHz operation. By using several processors and a ring network architecture, it can be enhanced up to 90 MCUPS.<<ETX>>