NoC Application Mapping Optimization Using Reinforcement Learning

Application mapping is one of the early stage design processes aimed to improve the performance of Network-on-Chip. Mapping is an NP-hard problem. A massive amount of high-quality supervised data is required to solve the application mapping problem using traditional neural networks. In this article, a reinforcement learning–based neural framework is proposed to learn the heuristics of the application mapping problem. The proposed reinforcement learning–based mapping algorithm (RL-MAP) has actor and critic networks. The actor is a policy network, which provides mapping sequences. The critic network estimates the communication cost of these mapping sequences. The actor network updates the policy distribution in the direction suggested by the critic. The proposed RL-MAP is trained with unsupervised data to predict the permutations of the cores to minimize the overall communication cost. Further, the solutions are improved using the 2-opt local search algorithm. The performance of RL-MAP is compared with a few well-known heuristic algorithms, the Neural Mapping Algorithm (NMA) and message-passing neural network-pointer network-based genetic algorithm (MPN-GA). Results show that the communication cost and runtime of the RL-MAP improved considerably in comparison with the heuristic algorithms. The communication cost of the solutions generated by RL-MAP is nearly equal to MPN-GA and improved by 4.2% over NMA, while consuming less runtime.

[1]  Yihua Huang,et al.  A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem , 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Yihua Huang,et al.  An IP Core Mapping Algorithm Based on Neural Networks , 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Xinyu Wang,et al.  An Effective Optimization Algorithm for Application Mapping in Network-on-Chip Designs , 2020, IEEE Transactions on Industrial Electronics.

[4]  Xiaojun Wang,et al.  KLSAT: An Application Mapping Algorithm Based on Kernighan-Lin Partition and Simulated Annealing for a Specific WK-Recursive NoC Architecture , 2019, NPC.

[5]  Juan Fang,et al.  Intelligent Mapping Method for Power Consumption and Delay Optimization Based on Heterogeneous NoC Platform , 2019, Electronics.

[6]  Santosh Biswas,et al.  Energy efficient heuristic application mapping for 2-D mesh-based network-on-chip , 2019, Microprocess. Microsystems.

[7]  Yi Liu,et al.  Unified multi-objective mapping for network-on-chip using genetic-based hyper-heuristic algorithms , 2018, IET Comput. Digit. Tech..

[8]  Alexandre Lacoste,et al.  Learning Heuristics for the TSP by Policy Gradient , 2018, CPAIOR.

[9]  Lukasz Kaiser,et al.  Attention is All you Need , 2017, NIPS.

[10]  Chenchen Deng,et al.  A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems , 2017, IEEE Transactions on Parallel and Distributed Systems.

[11]  Samy Bengio,et al.  Neural Combinatorial Optimization with Reinforcement Learning , 2016, ICLR.

[12]  Edwin Hsing-Mean Sha,et al.  Application Mapping and Scheduling for Network-on-Chip-Based Multiprocessor System-on-Chip With Fine-Grain Communication Optimization , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Santanu Chattopadhyay,et al.  A reliability aware application mapping onto mesh based Network-on-Chip , 2016, 2016 3rd International Conference on Recent Advances in Information Technology (RAIT).

[14]  Santanu Chattopadhyay,et al.  A constructive heuristic for application mapping onto an express channel based Network-on-Chip , 2015, 2015 19th International Symposium on VLSI Design and Test.

[15]  Chenchen Deng,et al.  An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Sergey Ioffe,et al.  Batch Normalization: Accelerating Deep Network Training by Reducing Internal Covariate Shift , 2015, ICML.

[17]  Jimmy Ba,et al.  Adam: A Method for Stochastic Optimization , 2014, ICLR.

[18]  Santanu Chattopadhyay,et al.  Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Abel G. Silva-Filho,et al.  An Ant Colony metaheuristic for energy aware application mapping on NoCs , 2013, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS).

[20]  Santanu Chattopadhyay,et al.  Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router , 2012, Microprocess. Microsystems.

[21]  Ozcan Ozturk,et al.  An ILP formulation for application mapping onto Network-on-Chips , 2009, 2009 International Conference on Application of Information and Communication Technologies.

[22]  Alexander Hall,et al.  Energy efficient application mapping to NoC processing elements operating at multiple voltage levels , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[23]  Santanu Chattopadhyay,et al.  Network-on-chip architecture design based on mesh-of-tree deterministic routing topology , 2008, Int. J. High Perform. Syst. Archit..

[24]  Berthold Vöcking,et al.  Worst Case and Probabilistic Analysis of the 2-Opt Algorithm for the TSP , 2007, SODA '07.

[25]  Krishnan Srinivasan,et al.  Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[26]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[27]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[28]  L. Carro,et al.  Time and energy efficient mapping of embedded applications onto NoCs , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[29]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[30]  Wayne H. Wolf,et al.  TGFF: task graphs for free , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[31]  Ronald J. Williams,et al.  Simple Statistical Gradient-Following Algorithms for Connectionist Reinforcement Learning , 2004, Machine Learning.

[32]  Lei Guo,et al.  A novel IP-core mapping algorithm in reliable 3D optical network-on-chips , 2018, Opt. Switch. Netw..

[33]  Santanu Chattopadhyay,et al.  A survey on application mapping strategies for Network-on-Chip design , 2013, J. Syst. Archit..

[34]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .