Optimal seed generation for delay fault detection BIST

In delay fault detection BIST (built-in-self-test), an adjacency test pattern generation scheme can generate robust test patterns effectively. Traditional adjacency test pattern generation schemes use an LFSR (linear feedback shift register) to generate initial vectors but they cannot handle circuits with more than 30 inputs. In this paper, a determined BIST scheme, where several seeds are applied, is proposed. Based on analysis of independent partial circuits in the circuit under test, an algorithm is used to generate the seeds - the small number of necessary initial vectors. Through combining outputs of the shift register, the number of shift register stages is reduced. Experiments show that the method of this paper has maximum fault coverage, and short test length that means short lest time. The hardware overhead is at the same level as traditional methods.

[1]  Charles R. Kime,et al.  Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults , 1985, International Test Conference.

[2]  M. Ray Mercer,et al.  A Deterministic Approach to Adjacency Testing for Delay Faults , 1989, 26th ACM/IEEE Design Automation Conference.

[3]  Yervant Zorian,et al.  On the generation of pseudo-deterministic two-patterns test sequence with LFSRs , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[4]  Karl Fuchs,et al.  A new BIST approach for delay fault testing , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[5]  Patrick Girard,et al.  An optimized BIST test pattern generator for delay testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[6]  Sandeep K. Gupta,et al.  Weighted random robust path delay testing of synthesized multilevel circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[7]  D. Michael Miller,et al.  BIST generators for sequential faults , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[8]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Sandeep K. Gupta,et al.  BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms , 1996, IEEE Trans. Computers.

[10]  Kwang-Ting Cheng,et al.  Delay fault testing for VLSI circuits , 1998 .

[11]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[12]  Karl Fuchs,et al.  A BIST approach to delay fault testing with reduced test length , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[13]  Constantin Halatsis,et al.  Accumulator-based BIST approach for stuck-open and delay fault testing , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.