MRAM-based memorization system for NB-LDPC decoder

This paper presents a novel implementation of the memorization system of the Non-Binary LDPC Decoder. The proposed approach relies on new implementations of STT-MRAM with power gating capabilities. A new data mapping has been defined to fit in with the physical dimensions of these implementations. The decoder adopting the devised memorization system has been compared to SRAM-based one which is used in almost all traditional decoders in order to demonstrate the feasibility of using power-gated MRAM. The obtained results show a significant reduction in the consumed energy by the memory reaching up to 78.45%.

[1]  David Declercq,et al.  Performance Evaluation of Non-Binary LDPC Codes on Wireless Channels , 2009 .

[2]  Vincent Gripon,et al.  NoC-MRAM architecture for memory-based computing: Database-search case study , 2017, 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS).

[3]  Ronald F. DeMara,et al.  Survey of STT-MRAM Cell Design Strategies , 2017, ACM J. Emerg. Technol. Comput. Syst..

[4]  D. Mackay,et al.  Low density parity check codes over GF(q) , 1998, 1998 Information Theory Workshop (Cat. No.98EX131).

[5]  Amir H. Banihashemi,et al.  On implementation of min-sum algorithm and its modifications for decoding low-density Parity-check (LDPC) codes , 2005, IEEE Transactions on Communications.

[6]  H. Ohno,et al.  A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme , 2013, IEEE Journal of Solid-State Circuits.

[7]  X. Jin.  Factor graphs and the Sum-Product Algorithm , 2002 .