Test and Repair Flow for Shared BISR in Asynchronous Multi-processors

We present a hierarchical test and repair flow for shared BISR (Built-In Self-Repair) in asynchronous multi-processors. The flow partitions the memories local to a processor in groups and treats the groups as a whole when doing the repair. The flow runs automatically with few interventions except at the beginning stage. It can be used effectively for practical industrial test and repair. Its test time is as good as equivalent to that of parallel BISR, while its test power is substantially lower, about 40% that of parallel repair. It also has a superior repair rate, about 11-12% better compared to sequential and parallel BISR.

[1]  Gang Wang A robust repair-aware test method for multi-memory , 2013, 2013 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP).

[2]  Keshab K. Parhi,et al.  Low power SRAM design using hierarchical divided bit-line approach , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[3]  Jin-Fu Li,et al.  ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Srinivas Raman,et al.  Direct access test scheme-design of block and core cells for embedded ASICs , 1990, Proceedings. International Test Conference 1990.

[5]  Sandip Kundu,et al.  Nanoscale CMOS VLSI Circuits: Design for Manufacturability , 2010 .

[6]  Krishnendu Chakrabarty,et al.  Optimal test access architectures for system-on-a-chip , 2001, TODE.

[7]  Liang Yang,et al.  Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.