Reconfigurable Real-Time Memory Controller Architecture

Background information on SDRAM technology is provided in Sect. 2.1. The properties of pattern-based memory controllers are introduced in Sect. 2.2. The story continues with a detailed description of our novel reconfigurable memory controller architecture in Sect. 2.3. In Sect. 2.4, we derive a worst-case performance model for this memory controller architecture, based on a Latency-rate server abstraction. We then continue with a discussion on the implementation of a hardware instance on FPGA in Sect. 2.5, followed by a cost evaluation in Sect. 2.6.

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