Logical modelling of delay degradation effect in static CMOS gates

A delay model for static CMOS gates with application in gate level logic simulation is presented. It incorporates the degradation effect on narrow pulses and is named PID (pure, inertial and degradation). The results lead to the conclusion that the proposed new delay model maintains the high speed of gate-level logic simulation with a precision comparable to that of electrical simulation.

[1]  J. Calvo,et al.  Metastable operation in RS flip-flops , 1991 .

[2]  Haigang Yang,et al.  Switch-level timing verification for CMOS circuits: a semianalytic approach , 1990 .

[3]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[4]  Nicholas C. Rumin,et al.  Inverter models of CMOS gates for supply current and delay evaluation , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  P. Hallam,et al.  CMOS process independent propagation delay macromodelling , 1995 .

[6]  Trevor Mudge,et al.  The impact of signal transition time on path delay computation , 1993 .

[7]  Kjell Jeppson,et al.  Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay , 1994 .

[8]  Stephen H. Unger,et al.  Asynchronous Sequential Switching Circuits with Unrestricted Input Changes , 1970, IEEE Transactions on Computers.

[9]  Michel Robert,et al.  Post-layout timing simulation of CMOS circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Y.-H. Jun,et al.  An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Antonio Rubio,et al.  Spurious signals in digital CMOS VLSI circuits: a propagation analysis , 1992 .

[12]  I. C. Teixeira,et al.  Physical macromodelling of the dynamic behaviour of CMOS VLSI circuits: Part II , 1992 .

[13]  Yan-Chyuan Shiau,et al.  Generic linear RC delay modeling for digital CMOS circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  L. Reyneri,et al.  Oscillatory metastability in homogeneous and inhomogeneous flip-flops , 1990 .

[15]  Elmar U. K. Melcher,et al.  Multiple input transitions in CMOS gates , 1992, Microprocess. Microprogramming.

[16]  Doris Schmitt-Landsiedel,et al.  Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..