Enabling New Computation Paradigms with HyperFET - An Emerging Device

High power consumption has significantly increased the cooling cost in high-performance computation stations and limited the operation time in portable systems powered by batteries. Traditional power reduction mechanisms have limited traction in the post-Dennard Scaling landscape. Emerging research on new computation devices and associated architectures has shown three trends with the potential to greatly mitigate current power limitations. The first is to employ steep-slope transistors to enable fundamentally more efficient operation at reduced supply voltage in conventional Boolean logic, reducing dynamic power. The second is to employ brain-inspired computation paradigms, directly embodying computation mechanisms inspired by the brains, which have shown potential in extremely efficient, if approximate, processing with silicon-neuron networks. The third is “let physics do the computation”, which focuses on using the intrinsic operation mechanism of devices (such as coupled oscillators) to do the approximate computation, instead of building complex circuits to carry out the same function. This paper first describes these three trends, and then proposes the use of the hybrid-phase-transition-FET (Hyper-FET), a device that could be configured as a steep-slope transistor, a spiking neuron cell, or an oscillator, as the device of choice for carrying these three trends forward. We discuss how a single class of device can be configured for these multiple use cases, and provide in-depth examination and analysis for a case study of building coupled-oscillator systems using Hyper-FETs for image processing. Performance benchmarking highlights the potential of significantly higher energy efficiency than dedicated CMOS accelerators at the same technology node.

[1]  Luis Ceze,et al.  Architecture support for disciplined approximate programming , 2012, ASPLOS XVII.

[2]  Narayanan Vijaykrishnan,et al.  Steep slope devices: Enabling new architectural paradigms , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[3]  S. Datta,et al.  Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[4]  A. Bermak,et al.  An 84 pW/Frame Per Pixel Current-Mode CMOS Image Sensor With Energy Harvesting Capability , 2012, IEEE Sensors Journal.

[5]  M. Spong,et al.  On Synchronization of Kuramoto Oscillators , 2005, Proceedings of the 44th IEEE Conference on Decision and Control.

[6]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[7]  Suman Datta,et al.  Synchronization of pairwise-coupled, identical, relaxation oscillators based on metal- insulator phase transition devices: A model study , 2014 .

[8]  Kaushik Roy,et al.  Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Arun V. Thathachary,et al.  A steep-slope transistor based on abrupt electronic phase transition , 2015, Nature Communications.

[10]  Suman Datta,et al.  Neuro inspired computing with coupled relaxation oscillators , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Charles T Rettner,et al.  Subnanosecond incubation times for electric-field-induced metallization of a correlated electron oxide. , 2014, Nature nanotechnology.

[12]  Robert M. Haralick,et al.  Integrated Directional Derivative Gradient Operator , 1987, IEEE Transactions on Systems, Man, and Cybernetics.

[13]  Narayanan Vijaykrishnan,et al.  Computational Architectures Based on Coupled Oscillators , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[14]  S. Datta,et al.  Pairwise coupled hybrid vanadium dioxide-MOSFET (HVFET) oscillators for non-boolean associative computing , 2014, 2014 IEEE International Electron Devices Meeting.

[15]  Yan Fang,et al.  Non-Boolean associative architectures based on nano-oscillators , 2012, 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications.

[16]  F. Corinto,et al.  An Associative Memory with oscillatory CNN arrays using spin torque oscillator cells and spin-wave interactions architecture and End-to-end Simulator , 2012, 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications.

[17]  Mahmut T. Kandemir,et al.  Steep-Slope Devices: From Dark to Dim Silicon , 2013, IEEE Micro.

[18]  Donald M. Chiarulli,et al.  HMAX image processing pipeline with coupled oscillator acceleration , 2014, 2014 IEEE Workshop on Signal Processing Systems (SiPS).

[19]  Myron Flickner,et al.  Compass: A scalable simulator for an architecture for cognitive computing , 2012, 2012 International Conference for High Performance Computing, Networking, Storage and Analysis.

[20]  Suman Datta,et al.  Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  S. Strogatz.  From Kuramoto to Crawford: exploring the onset of synchronization in populations of coupled oscillators , 2000 .

[22]  J. C. Kieffer,et al.  Evidence for a structurally-driven insulator-to-metal transition in VO 2 : A view from the ultrafast timescale , 2004, cond-mat/0403214.

[23]  DeLiang Wang,et al.  Image Segmentation Based on Oscillatory Correlation , 1997, Neural Computation.

[24]  Xueqing Li,et al.  Enabling Power-Efficient Designs with III-V Tunnel FETs , 2014, 2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

[25]  Renyuan Zhang,et al.  CMOS supporting circuitries for nano-oscillator-based associative memories , 2012, 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications.

[26]  DeLiang Wang,et al.  A dynamically coupled neural oscillator network for image segmentation , 2002, Neural Networks.

[27]  William Paul,et al.  Optical and transport properties of high quality crystals of V2O4 near the metallic transition temperature , 1969 .

[28]  Amine Bermak,et al.  A 12 pJ/Pixel Analog-to-Information Converter Based 816 × 640 Pixel CMOS Image Sensor , 2014, IEEE Journal of Solid-State Circuits.

[29]  S. Datta,et al.  Use of negative capacitance to provide voltage amplification for low power nanoscale devices. , 2008, Nano letters.

[30]  Narayanan Vijaykrishnan,et al.  Low-power high-speed current mode logic using Tunnel-FETs , 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

[31]  Suman Datta,et al.  NCFET Based Logic for Energy Harvesting Systems , 2015 .

[32]  Donald M. Chiarulli,et al.  An image processing pipeline using coupled oscillators , 2014, 2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA).

[33]  Narayanan Vijaykrishnan,et al.  Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[34]  Ron Kimmel,et al.  Efficient Dilation, Erosion, Opening and Closing Algorithms , 2000, ISMM.

[35]  Vijaykrishnan Narayanan,et al.  Synchronized charge oscillations in correlated electron systems , 2014, Scientific Reports.

[36]  Narayanan Vijaykrishnan,et al.  Rf-powered systems using steep-slope devices , 2014, 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS).

[37]  Katsuhiko Mori,et al.  Convolutional spiking neural network model for robust face detection , 2002, Proceedings of the 9th International Conference on Neural Information Processing, 2002. ICONIP '02..

[38]  Narayanan Vijaykrishnan,et al.  Tunnel FET RF Rectifier Design for Energy Harvesting Applications , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[39]  Firas A. Jassim.  Semi-Optimal Edge Detector based on Simple Standard Deviation with Adjusted Thresholding , 2013, ArXiv.

[40]  Yan Fang,et al.  Hierarchical Associative Memory Based on Oscillatory Neural Network , 2013 .

[41]  武藤 佳恭.  Neural network parallel computing , 1992 .

[42]  Yee Whye Teh,et al.  A Fast Learning Algorithm for Deep Belief Nets , 2006, Neural Computation.

[43]  C. Hu,et al.  Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation , 2011, 2011 International Electron Devices Meeting.

[44]  K. Kyamakya,et al.  A novel image processing approach combining a 'coupled nonlinear oscillators'-based paradigm with cellular neural networks for dynamic robust contrast enhancement , 2010, 2010 12th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010).

[45]  Jie Han,et al.  Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).

[46]  Dharmendra S. Modha,et al.  A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[47]  Donald M. Chiarulli,et al.  Image segmentation using frequency locking of coupled oscillators , 2014, 2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA).

[48]  Sander M. Bohte,et al.  Computing with Spiking Neuron Networks , 2012, Handbook of Natural Computing.

[49]  James M. Rehg,et al.  Statistical Color Models with Application to Skin Detection , 2004, International Journal of Computer Vision.

[50]  Ángel Rodríguez-Vázquez,et al.  Toward visual microprocessors , 2002, Proc. IEEE.