Design of High-Speed PWM Comparator for Class D Audio Power Amplifier

A high-speed comparator for PWM CMOS Class D audio power amplifiers was designed.In the comparator,a rail-to-rail structure was adopted for input stage,and the intermediate stage was composed of a latch and a self-biased differential amplifier,while an inverter was used as output stage.Because of its latch and self-biased amplifier structure,the comparator could drive large capacitive load in a very short time,satisfying the requirement of the subsequent circuit for driving capability.Based on BSIM3V3 Spice model of CSMC's 0.5 μm CMOS process,the comparator was simulated using Hspice.Results showed that,under the typical model,the circuit had a PSRR of 56 dB,a DC open-loop gain of 45 dB,an ICMR from-0.19 V to 4.93 V,and a transmission delay of 15 ns.