Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC

Due to the emergence of extremely high density memory along with the growing number of embedded memories, memory yield is an important issue. Memory self-repair using redundancies to increase the yield of memories is widely used. Because high density memories are vulnerable to soft errors, memory error correction code (ECC) plays an important role in memory design. In this paper, methods to exploit spare columns including replaced defective columns are proposed to improve memory ECC. To utilize replaced defective columns, the defect information needs to be stored. Two approaches to store defect information are proposed—one is to use a spare column and the other is to use a content-addressable-memory. Experimental results show that the proposed method can significantly enhance the ECC performance.

[1]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[2]  Ashok K. Agrawala,et al.  Fault Tolerant System Design , 1993 .

[3]  F. Lemmermeyer.  Error-correcting Codes , 2005 .

[4]  Michael Gössel,et al.  New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[5]  Chris Fallin,et al.  Memory power management via dynamic voltage/frequency scaling , 2011, ICAC '11.

[6]  Vincent C. Gaudet,et al.  High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

[7]  Umair Ishaq,et al.  Efficient Use of Unused Spare Columns to Improve Memory Error Correcting Rate , 2011, 2011 Asian Test Symposium.

[8]  W. W. Peterson,et al.  Error-Correcting Codes. , 1962 .

[9]  Meng-Fan Chang,et al.  17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[10]  Avijit Dutta,et al.  Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory , 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

[11]  Nur A. Touba,et al.  Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[12]  Nur A. Touba,et al.  Exploiting Unused Spare Columns to Improve Memory ECC , 2009, 2009 27th IEEE VLSI Test Symposium.

[13]  Yervant Zorian,et al.  Built in self repair for embedded high density SRAM , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  Vincent Gripon,et al.  Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  N. Rydbeck,et al.  PCM/TDMA satellite communication systems with error correcting and error detecting codes , 1976 .

[16]  Nur A. Touba.  Fault-Tolerant Design , 2008 .

[17]  Shuichi Sakai,et al.  Utilization of SECDED for soft error and variation-induced defect tolerance in caches , 2007 .

[18]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[19]  Shuichi Sakai,et al.  Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[20]  Sanu Mathew,et al.  A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[21]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.

[22]  Guangxin Zhang,et al.  Fault Tolerant System Design Based Fuzzy Observer , 2006, PROLAMAT.

[23]  Valentin Gherman,et al.  Programmable extended SEC-DED codes for memory errors , 2011, 29th VLSI Test Symposium.