Weighted $p$ -Bits for FPGA Implementation of Probabilistic Circuits

Probabilistic spin logic is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (<inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve the problems of optimization, inference, and implement precise Boolean functions in an “inverted” mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this brief, we present a scalable field-programmable gate array implementation of such invertible p-circuits. We implement a “weighted” <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-bits to which a large class of problems beyond invertible Boolean logic can be mapped and how invertibility can be applied to interesting problems such as the NP-complete subset sum problem by solving a small instance of this problem in hardware.

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