Message routing in 3D networks-on-chip

Nowadays 3D chips are fabricated by stacking 2D layers and manufacturing vertical links between them. In this paper we present a routing scheme suited for 3D networks-on-chip (NoCs). It is based on the reuse of existing routing schemes for 2D NoCs. Our 3D scheme is scalable and can be used with any 2D topology. The effectiveness of the scheme for intra-layer communication is given by the respective 2D routing scheme of each layer, while for the inter-layer communication the scheme can always find a route between any source and destination, if there is one available.

[1]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Indranil Gupta,et al.  JetStream: Achieving Predictable Gossip Dissemination by Leveraging Social Network Principles , 2006, Fifth IEEE International Symposium on Network Computing and Applications (NCA'06).

[3]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[4]  Shietung Peng,et al.  Adaptive box-based efficient fault-tolerant routing in 3D torus , 2005, 11th International Conference on Parallel and Distributed Systems (ICPADS'05).

[5]  Anantha Chandrakasan,et al.  Three-dimensional integrated circuits: performance, design methodology, and CAD tools , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[6]  Jie Wu,et al.  Fault-tolerant routing in meshes/tori using planarly constructed fault blocks , 2005, 2005 International Conference on Parallel Processing (ICPP'05).

[7]  C.M. Cunningham,et al.  Fault-tolerant adaptive routing for two-dimensional meshes , 1995, Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture.

[8]  Antonio Robles,et al.  A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes , 2004, NPC.

[9]  Jie Wu,et al.  A simple fault-tolerant adaptive and minimal routing approach in 3-D meshes , 2008, Journal of Computer Science and Technology.

[10]  L. Anghel,et al.  A flexible network-on-chip simulator for early design space exploration , 2008, 2008 1st Microsystems and Nanoelectronics Research Conference.

[11]  Luca Benini,et al.  A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, ICCAD 2008.