Accurate determination of channel length, series resistance and junction doping profile for MOSFET optimisation in deep submicron technologies

A new single transistor method to determine both the junction spacing (Lmet) and the parasitic series resistance (Rs) is presented. An extension of this new method allows for the first time to extract the lateral S/D junction doping profile under the poly gate. Measurements of individual devices with poly lengths ranging from 10 /spl mu/m down to 0.07 /spl mu/m reveal that conventional extraction methods can make significant errors for Lmet up to 150 nm, which is unacceptable for the characterisation of 0.25 /spl mu/m technologies and below. The resolution of the new method is around 10-15 nm, sufficient to investigate and optimise our fabricated 0.1 /spl mu/m MOS-devices.

[1]  S. Laux,et al.  Accuracy of an effective channel length/External resistance extraction algorithm for MOSFET's , 1984, IEEE Transactions on Electron Devices.

[2]  G.J. Hu,et al.  Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's , 1987, IEEE Transactions on Electron Devices.

[3]  K. Ng,et al.  The impact of intrinsic series resistance on MOSFET scaling , 1986, IEEE Transactions on Electron Devices.

[4]  Y. Taur,et al.  A new 'shift and ratio' method for MOSFET channel-length extraction , 1992, IEEE Electron Device Letters.