Dual band CMOS LNA design with current reuse topology

A dual band receiver architecture is introduced; it is able to make simultaneous operations at two different frequency bands. This architecture uses a dual band low noise amplifier (LNA). A novel high gain and low noise amplifier topology is proposed. This paper presents a general methodology to design an LNA with current reuse topology for the two standards GSM and UMTS at 947.5 MHz and 2.14 GHz frequencies, respectively. A fully integrated dual band LNA was designed using 0.35 µm CMOS process. At 947.5 MHz, the LNA exhibits a noise figure of 2.3 dB, a voltage gain of 28 dB and CP1 of −12 dBm. However, the LNA at 2.14 GHz features a noise figure of 2.71 dB, a voltage gain of 17 dB and a CP1 of −4.5 dBm. The power consumption is 37.5 mW under a power supply voltage of 2.5 V.

[1]  B. Razavi,et al.  A 900 MHz/1.8 GHz CMOS receiver for dual band applications , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[2]  J. Imbornone,et al.  Fully differential dual-band image reject receiver in SiGe BiCMOS , 2000, 2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096).

[3]  A. Karanicolas.  A 2.7 V 900 MHz CMOS LNA and mixer , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[4]  S. Moinian,et al.  High Q inductors for wireless applications in a complementary silicon bipolar process , 1996 .

[5]  A. Abidi,et al.  Large suspended inductors on silicon and their use in a 2- mu m CMOS RF amplifier , 1993, IEEE Electron Device Letters.

[6]  Hyungcheol Shin,et al.  Simple wide-band on-chip inductor model for silicon-based RF ICs , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

[7]  Ali M. Niknejad,et al.  Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs , 1998, IEEE J. Solid State Circuits.

[8]  T.H. Lee,et al.  A physical model for planar spiral inductors on silicon , 1996, International Electron Devices Meeting. Technical Digest.

[9]  Ming-Jer Chen,et al.  Characterization and modeling of on-chip inductor substrate coupling effect , 2002, 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280).

[10]  Pietro Andreani,et al.  Noise optimization of an inductively degenerated CMOS low noise amplifier , 2001 .

[11]  Bonkee Kim,et al.  Monolithic planar RF inductor and waveguide structures on silicon with performance comparable to those in GaAs MMIC , 1995, Proceedings of International Electron Devices Meeting.

[12]  A. Niknejad,et al.  Analysis , Design , and Optimization of Spiral Inductors and Transformers for Si RF IC ’ s , 1998 .

[13]  Hossein Hashemi,et al.  Concurrent multiband low-noise amplifiers-theory, design, and applications , 2002 .

[14]  Choong-Yul Cha,et al.  A low power, high gain LNA topology , 2000, ICMMT 2000. 2000 2nd International Conference on Microwave and Millimeter Wave Technology Proceedings (Cat. No.00EX364).

[15]  K. O. Kenneth,et al.  A dual-band CMOS front-end with two gain modes for wireless LAN applications , 2004, IEEE Journal of Solid-State Circuits.

[16]  Rahul Magoon,et al.  A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digital wireless communication , 1999 .

[17]  J. Long,et al.  The modeling, characterization, and design of monolithic inductors for silicon RF IC's , 1997, IEEE J. Solid State Circuits.