Devices' optimization against hot-carrier degradation in high voltage pLEDMOS transistor

The degradations of p-type lateral extended drain MOS transistors with thick gate oxide are experimentally investigated. To decrease the hot-carrier degradation, two methods are proposed to optimize the drift region without additional processes. The novel structure is with a low doped boundary of the drift region and a drift region implanted at intervals by multi-windows, which will be helpful in reducing the electric field, reducing the degradations of electrical parameters correspondingly. The effects have been detailed analyzed by the CP measurements and TCAD simulations. Out of the simulations results, the length of the low doped boundary and the space between the doping windows of the sub-drifts are discussed, and their effects on the degradation induced by hot carriers has been investigated in detailed. An optimization structure is proposed for the first time.