Process Variation Analysis and Optimization of a FinFET-Based VCO

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS for nanoscale technologies. In this paper, the viability of a mixed-signal design for FinFET-based technologies using a nanoscale current-starved voltage controlled oscillator (VCO) is investigated. Design issues are analyzed and a comparison between a CMOS VCO and a FinFET-based VCO is presented. The figures-of-merit used for comparison are center frequency and frequency–voltage (<inline-formula> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>) characteristics under process variation. Models are developed for the <inline-formula> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics of both the CMOS and FinFET VCOs. In addition, width quantization-aware modeling has been performed for the FinFET-based VCO using a polynomial metamodel, which can be used for further optimization. The quantization aware modeling is highly accurate as evident from a correlation coefficient <inline-formula> <tex-math notation="LaTeX">${R^{2}}$ </tex-math></inline-formula> of 0.999 and root mean square error of 6.2 MHz. The FinFET VCO has <inline-formula> <tex-math notation="LaTeX">$5.5 {\times }$ </tex-math></inline-formula> faster oscillation frequency with 2.6% variability as opposed to 19.7% for the CMOS VCO. To the best of the authors’ knowledge, this is the first paper that examines FinFET technology with respect to process variation in mixed signal designs at the circuit level, and presents a quantitative as well as qualitative comparison between CMOS and FinFET technologies.

[1]  Soha Hassoun,et al.  Gate sizing: finFETs vs 32nm bulk MOSFETs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[2]  H. Sjoland,et al.  High performance 1 V 2.4 GHz CMOS VCO , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[3]  Saraju P. Mohanty,et al.  Double gate FinFET based mixed-signal design: A VCO case study , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

[4]  George Varghese,et al.  A 22nm IA multi-CPU and GPU System-on-Chip , 2012, 2012 IEEE International Solid-State Circuits Conference.

[5]  William Rhett Davis,et al.  FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology , 2015, ISPD.

[6]  Robert J. Weber,et al.  A 2.4GHz low-power low-phase-noise CMOS LC VCO , 2004, IEEE Computer Society Annual Symposium on VLSI.

[7]  Dhiraj K. Pradhan,et al.  P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[8]  Rasoul Dehghani,et al.  Optimised analytic designed 2.5 GHz CMOS VCO , 2003 .

[9]  Zhiyu Liu,et al.  Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[10]  Saraju P. Mohanty,et al.  Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs , 2014, IEEE Transactions on Semiconductor Manufacturing.

[11]  Runze Li,et al.  Design and Modeling for Computer Experiments (Computer Science & Data Analysis) , 2005 .

[12]  Saraju P. Mohanty,et al.  Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO , 2009, GLSVLSI '09.

[13]  B.C. Paul,et al.  Process variation in embedded memories: failure analysis and variation aware architecture , 2005, IEEE Journal of Solid-State Circuits.

[14]  Yu Cao,et al.  Optimizing finfet technology for high-speed and low-power design , 2007, GLSVLSI '07.

[15]  S. Kaya,et al.  A novel voltage-controlled ring oscillator based on nanoscale DG-MOSFETs , 2008, 2008 International Conference on Microelectronics.

[16]  G. A. Armstrong,et al.  Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications , 2007, IEEE Transactions on Electron Devices.

[17]  Mayler G. A. Martins,et al.  Open Cell Library in 15nm FreePDK Technology , 2015, ISPD.

[18]  Jie Gu,et al.  Width Quantization Aware FinFET Circuit Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[19]  Rajiv V. Joshi,et al.  FinFET SRAM Design , 2010, 2010 23rd International Conference on VLSI Design.

[20]  Dhiraj K. Pradhan,et al.  Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM , 2012, Integr..

[21]  Niraj K. Jha,et al.  3D vs. 2D analysis of FinFET logic gates under process variations , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[22]  Andrew R. Brown,et al.  Statistical variability and reliability in nanoscale FinFETs , 2011, 2011 International Electron Devices Meeting.

[23]  Saraju P. Mohanty,et al.  Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Ganapati Panda,et al.  A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO , 2014, IEEE Transactions on Semiconductor Manufacturing.

[25]  Saraju P. Mohanty,et al.  Variability-aware design of double gate FinFET-based current mirrors , 2014, GLSVLSI '14.

[26]  H.C. Luong,et al.  Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback , 2005, IEEE Journal of Solid-State Circuits.

[27]  Anish Muttreja,et al.  CMOS logic design with independent-gate FinFETs , 2007, 2007 25th International Conference on Computer Design.

[28]  Niraj K. Jha,et al.  Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology , 2012, 2012 25th International Conference on VLSI Design.

[29]  Saraju P. Mohanty,et al.  A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO , 2010, 2010 23rd International Conference on VLSI Design.

[30]  Farshad Moradi,et al.  Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective , 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

[31]  K. Endo,et al.  Comprehensive analysis of variability sources of FinFET characteristics , 2006, 2009 Symposium on VLSI Technology.

[32]  Hesham F. A. Hamed,et al.  Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[33]  Yuan Xie,et al.  Dependability analysis of nano-scale FinFET circuits , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).