MPEG-4 및 H.264 통합 비디오 디코더를 위한 IQ/IDCT 회로 구조

In this paper we propose the circuit architecture to integrate inverse transform and inverse quantization for MPEG-4 and H.264 decoder. The circuit architecture of integrated inverse transform is based on the inverse DCT circuit of MPEG-4. Among the resource blocks in the inverse DCT circuit of MPEG-4, eight adders are shared with the inverse transform circuit of H.264. The integrated inverse quantization circuit shares one multiplier. The control logic was added to the integrated inverse transform and inverse quantization circuit. Based on the proposed architecture, we designed the register transfer level circuit in Verilog HDL. This circuit was verified using NC-Veri log and synthesized with Synopsys Design Complier. Our circuit is efficient in terms of area, still maintaining a real-time processing capability for the images of D1 size.