Design of floating point units for interval arithmetic

In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed architecture is based on a dual result multiplier (floating point multiplication unit with two differently rounded results for the same pair of operands) and two floating point comparators. The goal of the divide-add fused unit is to increase the performance of the interval Newton's method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed.

[1]  Gregory B. Zyner,et al.  167 MHz radix-8 divide and square root using overlapped radix-2 stages , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[2]  Mircea Vladutiu,et al.  Floating point multiplication rounding schemes for interval arithmetic , 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

[3]  Earl E. Swartzlander,et al.  Hardware design and arithmetic algorithms for a variable-precision, interval arithmetic coprocessor , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[4]  Ulrich W. Kulisch.  Advanced Arithmetic for the Digital Computer , 2002 .

[5]  Earl E. Swartzlander,et al.  A variable-precision interval arithmetic processor , 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).

[6]  Peter-Michael Seidel,et al.  Delay-optimized implementation of IEEE floating-point addition , 2004, IEEE Transactions on Computers.

[7]  Neil Burgess,et al.  Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell , 2007, 18th IEEE Symposium on Computer Arithmetic (ARITH '07).

[8]  EvenGuy,et al.  Delay-Optimized Implementation of IEEE Floating-Point Addition , 2004 .

[9]  T. Lang,et al.  Floating-point fused multiply-add with reduced latency , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[10]  Ahmet Akkas.  A combined interval and floating-point comparator/selector , 2002, Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors.

[11]  Peter Kornerup.  Digit selection for SRT division and square root , 2005, IEEE Transactions on Computers.

[12]  Gregory B. Zyner,et al.  167 MHz radix-4 floating point multiplier , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[13]  Javier D. Bruguera,et al.  Floating-point fused multiply-add: reduced latency for floating-point addition , 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).

[14]  Mircea Vladutiu,et al.  Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition , 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

[15]  Michael J. Schulte,et al.  A combined interval and floating point multiplier , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[16]  B. Hayes.  The American Scientist , 1962, Nature.

[17]  Michael J. Flynn,et al.  High-performance arithmetic for division and the elementary functions , 2002 .

[18]  Michael J. Flynn,et al.  Design Issues in Division and Other Floating-Point Operations , 1997, IEEE Trans. Computers.

[19]  Stuart Franklin Oberman,et al.  Design issues in high performance floating point arithmetic units , 1996 .

[20]  Inmaculada García,et al.  Reliable algorithms for ray intersection in computer graphics based on interval arithmetic , 2003, 16th Brazilian Symposium on Computer Graphics and Image Processing (SIBGRAPI 2003).

[21]  Peter-Michael Seidel,et al.  A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication , 2000, IEEE Trans. Computers.

[22]  James E. Stine,et al.  A combined interval and floating-point comparator , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[23]  Peter-Michael Seidel.  On the design of IEEE compliant floating point units and their quantitative analysis , 1999 .

[24]  R. B. Kearfott,et al.  Interval Computations: Introduction, Uses, and Resources , 2000 .

[25]  Ulrich W. Kulisch,et al.  Hardware Support for Interval Arithmetic , 2006, Reliab. Comput..

[26]  N. Quach,et al.  On fast IEEE rounding , 1991 .