论文信息 - A low-power 14-bit two-stage hybrid ADC for infrared focal plane array detector

A low-power 14-bit two-stage hybrid ADC for infrared focal plane array detector

This paper presents a low-power 14-bit hybrid incremental Σ-Δ/cyclic analog-to-digital converter (ADC) based on pseudo-differential operational amplifier, which is designed for the readout circuit of infrared focal plane array detector. This two-stage hybrid ADC employs an incremental sigma-delta ADC and a cyclic ADC, achieving a good trade-off between accuracy and conversion speed. The two stages share the same analog circuit to reduce area and power consumption. A common-mood feedback module is used to suppress the influence of charge injection, and the effectiveness is demonstrated by detailed theoretical analysis and simulation result. A test chip is fabricated in 0.18 μm CMOS technology. The hybrid ADC in each column is performed in parallel with power consumption of 218.813 μW The simulation result reveals the effective number of bits (ENOB) is 13.775 bits.

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