Threshold Voltage Variations Make Full Adders Reliabilities Similar

Addition is the most widely used arithmetic operation in digital applications. The reliability of full adder (FA) cells is crucial as they affect arithmetic logic and floating-point units, as well as cache/memory address calculations. This letter studies the reliability of five different FA designs. The analysis starts from the device level by estimating the effects threshold voltage variations will have on the reliability of scaled CMOS transistors. These estimations will then be used to calculate the reliability of the sum and carry_out signals. This letter will also briefly explore the effects of increasing the reliability of devices and of using gate-level redundancy schemes on the reliability of FAs.

[1]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .

[2]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[3]  V. Beiu,et al.  On the Reliability of Majority Gates Full Adders , 2008, IEEE Transactions on Nanotechnology.

[4]  Byung-Gook Park,et al.  Comparative study on the energy efficiency of logic gates based on single-electron transistor technology , 2009 .

[5]  H. Iwai,et al.  Roadmap for 22 nm and beyond , 2009 .

[6]  A. Asenov,et al.  Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability , 2008, IEEE Electron Device Letters.

[7]  Y. Leblebici,et al.  Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies , 2009, IEEE Transactions on Nanotechnology.

[8]  Martin Margala,et al.  New performance/power/area efficient, reliable full adder design , 2009, GLSVLSI '09.

[9]  D.V. Anderson,et al.  Increased energy efficiency and reliability of ultra-low power arithmetic , 2008, 2008 51st Midwest Symposium on Circuits and Systems.

[10]  Peter M. Kogge,et al.  Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Magdy A. Bayoumi,et al.  Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Snorre Aunet,et al.  Six subthreshold full adder cells characterized in 90 nm CMOS technology , 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

[13]  Ismo Hänninen,et al.  Reliability of n-Bit Nanotechnology Adder , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[14]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[15]  Valeriu Beiu,et al.  A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations , 2009, NanoNet.

[16]  Hiroshi Iwai,et al.  Roadmap for 22nm and beyond (Invited Paper) , 2009 .

[17]  Theresa F. Klaschka.  A Method for Redundancy Scheme Performance Assessment , 1971, IEEE Transactions on Computers.