Improving PCM Endurance with a Constant-Cost Wear Leveling Design

Improving PCM endurance is a fundamental issue when it is considered as an alternative to replace DRAM as main memory. Memory-based wear leveling (WL) is an effective way to improve PCM endurance, but its major challenge is how to efficiently determine the appropriate memory pages for allocation or swapping. In this article, we present a constant-cost WL design that is compatible with existing memory management. Two implementations, namely bucket-based and array-based WL, with constant-time (or nearly zero) search cost are proposed to be integrated into the OS layer and the hardware layer, respectively, as well as to trade between time and space complexity. The results of experiments conducted based on an implementation in Android, as well as simulations with popular benchmarks, to evaluate the effectiveness of the proposed design are very encouraging.

[1]  Hsien-Hsin S. Lee,et al.  Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping , 2010, ISCA.

[2]  Liang Shi,et al.  Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory , 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

[3]  Rami G. Melhem,et al.  Using PCM in Next-generation Embedded Space Applications , 2010, 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium.

[4]  Liang Shi,et al.  Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Mohammad Arjomand,et al.  Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing , 2015, TODE.

[6]  Qingfeng Zhuge,et al.  Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  H. Howie Huang,et al.  Energy-aware writes to non-volatile main memory , 2011, OPSR.

[8]  Luis A. Lastras,et al.  Practical and secure PCM systems by online detection of malicious write streams , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[9]  Zili Shao,et al.  Towards Write-Activity-Aware Page Table Management for Non-volatile Main Memories , 2015, TECS.

[10]  Hongliang Yu,et al.  Increasing Endurance and Security of Phase-Change Memory with Multi-Way Wear-Leveling , 2014, IEEE Transactions on Computers.

[11]  Karin Strauss,et al.  Use ECP, not ECC, for hard failures in resistive memories , 2010, ISCA.

[12]  Edwin Hsing-Mean Sha,et al.  Building high-performance smartphones via non-volatile memory: The swap approach , 2014, 2014 International Conference on Embedded Software (EMSOFT).

[13]  Zili Shao,et al.  A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  Tei-Wei Kuo,et al.  Age-based PCM wear leveling with nearly zero search cost , 2012, DAC Design Automation Conference 2012.

[15]  Rami G. Melhem,et al.  Increasing PCM main memory lifetime , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[16]  Wei-Che Tseng,et al.  Software enabled wear-leveling for hybrid PCM main memory on embedded systems , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[17]  David Hung-Chang Du,et al.  Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead , 2011, 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST).

[18]  Tei-Wei Kuo,et al.  An adaptive striping architecture for flash memory storage systems of embedded systems , 2002, Proceedings. Eighth IEEE Real-Time and Embedded Technology and Applications Symposium.

[19]  Vijayalakshmi Srinivasan,et al.  Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[20]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

[21]  Yi He,et al.  Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation , 2010, Design Automation Conference.

[22]  Sivan Toledo,et al.  Algorithms and data structures for flash memories , 2005, CSUR.

[23]  Xiaowei Li,et al.  Wear rate leveling: Lifetime enhancement of PRAM with endurance variation , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[24]  吉田 則裕,et al.  Android Open Source Projectを対象としたパッチレビュー活動の調査 , 2012 .

[25]  Vijayalakshmi Srinivasan,et al.  Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.

[26]  Hyunjin Lee,et al.  Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[27]  Hai Zhou,et al.  Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems , 2010 .

[28]  Tei-Wei Kuo,et al.  Marching-Based Wear-Leveling for PCM-Based Storage Systems , 2015, TODE.

[29]  H. Howie Huang,et al.  Energy-aware writes to non-volatile main memory , 2011, ACM SIGOPS Oper. Syst. Rev..

[30]  Westone,et al.  Home Page , 2004, 2022 2nd International Conference on Intelligent Cybernetics Technology & Applications (ICICyTA).

[31]  Tei-Wei Kuo,et al.  Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[32]  Wei-Che Tseng,et al.  Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories , 2014, IEEE Transactions on Computers.

[33]  Li-Pin Chang,et al.  On efficient wear leveling for large-scale flash-memory storage systems , 2007, SAC '07.

[34]  Tao Li,et al.  Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures , 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.

[35]  Jun Yang,et al.  A durable and energy efficient main memory using phase change memory technology , 2009, ISCA '09.

[36]  Jun Yang,et al.  LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory , 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems & Networks (DSN).

[37]  Tao Li,et al.  Characterizing and mitigating the impact of process variations on phase change based memory systems , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[38]  Norman P. Jouppi,et al.  FREE-p: Protecting non-volatile memory against both hard and soft errors , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[39]  Chun Jason Xue,et al.  SLC-enabled wear leveling for MLC PCM considering process variation , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).