Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications

Approximate computing paradigm has emerged as one of the key research fields in area and energy efficient CMOS circuit design for error-tolerant applications like data mining, scientific computing, multimedia applications, etc. Multimedia applications (such as H.264) which use SRAM as storage consume a significant amount of power. In this paper, we propose heterogeneous 8T SRAM memory architectures without and with truncation (2-bit) as storage for low power multimedia applications in smartphones. To the best of our knowledge, this is the first work where both heterogeneous SRAM design and bit-truncation techniques have been simultaneously used to obtain low power memory design for multimedia applications. We show that the proposed techniques provide high image quality even at low power and low area budget of 0.3 uW/pixel and 5.2 um^2/pixel at 0.5 V and 20 MHz in UMC 28nm. The proposed memory architecture is compared with existing heterogeneous 6T, hybrid 8T/6T, all-identical 6T, and all-identical 8T SRAM memory. The results show that proposed memory architectures perform cumulatively better than existing techniques in terms of dynamic power, leakage power & area. The use of proposed memory for storage of an image has much higher Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index Metric (SSIM) than existing SRAM techniques. The results are verified by Spice simulation performed in UMC 28 nm CMOS technology.