Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models

This paper proposes a technique for extracting an instruction scheduler from a LISA processor description. The generated tool reads unscheduled, sequential assembly code from a C compiler. It schedules the instructions using an efficient backtracking scheduling algorithm that allows automated delay slot filling and utilization of instruction level parallelism. For an industrial network processor and a multimedia VLIW architecture the quality of the generated assembly code is compared to that of compilers with handwritten scheduler specifications.

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