A survey of research and practices of Network-on-chip

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

[1]  共立出版株式会社.  コンピュータ・サイエンス : ACM computing surveys , 1978 .

[2]  Daniel Marcos Chapiro,et al.  Globally-asynchronous locally-synchronous systems , 1985 .

[3]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[4]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[5]  Yuval Tamir,et al.  High-performance multiqueue buffers for VLSI communication switches , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

[6]  Y. Tamir,et al.  High-performance multi-queue buffers for VLSI communications switches , 1988, ISCA '88.

[7]  William J. Dally,et al.  Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[8]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[9]  William J. Dally,et al.  Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels , 1993, IEEE Trans. Parallel Distributed Syst..

[10]  José Duato,et al.  A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks , 1993, IEEE Trans. Parallel Distributed Syst..

[11]  José Duato,et al.  994 International Conference on Parallel Processing a Necessary and Sufficient Condition for Deadlock-free Adaptive Routing in Wormhole Networks , 2022 .

[12]  A. El Gamal,et al.  Regenerative feedback repeaters for programmable interconnections , 1995 .

[13]  José Duato.  A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks , 1995, IEEE Trans. Parallel Distributed Syst..

[14]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[15]  Richard Cole,et al.  On the benefit of supporting virtual channels in wormhole routers , 1996, SPAA '96.

[16]  M.A. Horowitz,et al.  A 50% noise reduction interface using low-weight coding , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[17]  Sudhakar Yalamanchili,et al.  Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks , 1996, IEEE Trans. Computers.

[18]  José Duato,et al.  A Necessary and Sufficient Condition for Deadlock-Free Routing in Cut-Through and Store-and-Forward Networks , 1996, IEEE Trans. Parallel Distributed Syst..

[19]  W. Heinrich,et al.  Thin-film microstrip lines for MM and sub-MM/wave on-chip interconnects , 1997, 1997 IEEE MTT-S International Microwave Symposium Digest.

[20]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[21]  K.M. Al-Tawil,et al.  A survey and comparison of wormhole routing techniques in a mesh networks , 1997, IEEE Network.

[22]  Minyi Guo,et al.  Contention-free communication scheduling for array redistribution , 1998, Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250).

[23]  William J. Dally,et al.  A bandwidth-efficient architecture for media processing , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[24]  H. Wijshoff,et al.  A quantitative comparison of parallel computation models , 1998, TOCS.

[25]  The Turn Model for Adaptive Routing , 1998, 25 Years ISCA: Retrospectives and Reprints.

[26]  Anoop Gupta,et al.  Parallel computer architecture - a hardware / software approach , 1998 .

[27]  K. Ken Lee.  On-chip interconnects -gigahertz and beyond , 1998 .

[28]  Hannu Tenhunen,et al.  Globally asynchronous locally synchronous architecture for large high-performance ASICs , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[29]  Steven M. Nowick,et al.  High-throughput asynchronous pipelines for fine-grain dynamic datapaths , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[30]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[31]  Sujit Dey,et al.  Communication architecture tuners: a methodology for the design of high-performance communication architectures for system-on-chips , 2000, Proceedings 37th Design Automation Conference.

[32]  Kurt Keutzer,et al.  A global wiring paradigm for deep submicron design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  William J. Dally,et al.  Flit-reservation flow control , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

[34]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[35]  Russell Tessier,et al.  ASOC: a scalable, single-chip communications architecture , 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).

[36]  William J. Dally,et al.  Smart Memories: a modular reconfigurable architecture , 2000, ISCA '00.

[37]  H. Zhang,et al.  A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[38]  Wolfgang Fichtner,et al.  Practical design of globally-asynchronous locally-synchronous systems , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[39]  Minyi Guo,et al.  Contention-free communication scheduling for array redistribution , 2000, Parallel Comput..

[40]  George Varghese,et al.  Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[41]  C. Svensson.  Optimum voltage swing on on-chip and off-chip interconnects , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[42]  Richard Cole,et al.  On the Benefit of Supporting Virtual Channels in Wormhole Routers , 2001, J. Comput. Syst. Sci..

[43]  R. H. Havemann,et al.  High-performance interconnects: an integration overview , 2001, Proc. IEEE.

[44]  Sujit Dey,et al.  Evaluation of the traffic-performance characteristics of system-on-chip communication architectures , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[45]  N.A. Kurd,et al.  Multi-GHz clocking scheme for Intel(R) Pentium(R) 4 microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[46]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[47]  Sujit Dey,et al.  On-chip communication architecture for OC-768 network processors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[48]  M. Mizuno,et al.  Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[49]  T. Xanthopoulos,et al.  The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[50]  Kees Goossens,et al.  A Router Architecture for Networks on Silicon , 2001 .

[51]  Chita R. Das,et al.  Impact of virtual channels and adaptive routing on application performance , 2001, SIGCPR '01.

[52]  Steven M. Nowick,et al.  Robust interfaces for mixed-timing systems with application to latency-insensitive protocols , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[53]  Alessandro Bogliolo.  Encodings for high-performance for energy-efficient signaling , 2001, ISLPED '01.

[54]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[55]  Jens Sparsø,et al.  Principles of Asynchronous Circuit Design , 2001 .

[56]  Luca Benini,et al.  Powering networks on chips , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[57]  William John Bainbridge,et al.  Delay insensitive system-on-chip interconnect using 1-of-4 data encoding , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

[58]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[59]  José Duato,et al.  A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources , 2001, IEEE Trans. Parallel Distributed Syst..

[60]  William J. Dally,et al.  A Delay Model for Router Microarchitectures , 2001, IEEE Micro.

[61]  Kees G. W. Goossens,et al.  Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[62]  Radu Marculescu,et al.  Traffic analysis for on-chip networks design of multimedia applications , 2002, DAC '02.

[63]  Martti Forsell,et al.  A Scalable High-Performance Computing Solution for Networks on Chips , 2002, IEEE Micro.

[64]  Kees G. W. Goossens,et al.  Networks on silicon: blessing or nightmare? , 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.

[65]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[66]  Managing power consumption in networks on chips , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[67]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[68]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[69]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[70]  Stephen B. Furber,et al.  Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.

[71]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[72]  Orion: a power-performance simulator for interconnection networks , 2002, MICRO 35.

[73]  Vojin G. Oklobdzija,et al.  Future directions in clocking multi-ghz systems , 2002, ISLPED '02.

[74]  Manoj Franklin,et al.  Hierarchical interconnects for on-chip clustering , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[75]  Ran Ginosar.  Fourteen ways to fool your synchronizer , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[76]  A. Gerstlauer.  Communication Abstractions for System-Level Design and Synthesis , 2003 .

[77]  Kees Goossens,et al.  Concepts and Implementation of the Philips Network-on-Chip , 2003 .

[78]  T. Felicijan,et al.  An asynchronous low latency arbiter for Quality of Service (QoS) applications , 2003, Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442).

[79]  Axel Jantsch,et al.  Networks on chip , 2003 .

[80]  Rabi N. Mahapatra,et al.  Interfacing cores with on-chip packet-switched networks , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[81]  V.G. Oklobdzija,et al.  A clock skew absorbing flip-flop , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[82]  P. Kapur,et al.  Optical interconnects for future high performance integrated circuits , 2003 .

[83]  Johnny Öberg.  Clocking Strategies for Networks-on-Chip , 2003, Networks on Chip.

[84]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[85]  Alain Greiner,et al.  Micro-network for SoC: implementation of a 32-port SPIN network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[86]  Axel Jantsch,et al.  A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[87]  Axel Jantsch,et al.  Communication Performance in Network-on-Chips , 2003 .

[88]  M. Horowitz,et al.  Efficient on-chip global interconnects , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[89]  Jan Madsen,et al.  Network-on-chip modeling for system-level multiprocessor simulation , 2003, RTSS 2003. 24th IEEE Real-Time Systems Symposium, 2003.

[90]  Dake Liu,et al.  Design of a switching node (router) for on-chip networks , 2003, ASIC, 2003. Proceedings. 5th International Conference on.

[91]  Partha Pratim Pande,et al.  Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[92]  Tapani Ahonen,et al.  Topology optimization for application-specific networks-on-chip , 2004, SLIP '04.

[93]  Luca Benini,et al.  ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip , 2004, DATE.

[94]  Rudy Lauwereins,et al.  How can system level design solve the interconnect technology scaling problem? , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[95]  Karam S. Chatha,et al.  A power and performance model for network-on-chip architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[96]  Axel Jantsch,et al.  Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[97]  Radu Marculescu,et al.  Application-specific buffer space allocation for networks-on-chip router design , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[98]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[99]  Jari Nurmi,et al.  Packet scheduling in proteo network-on-chip , 2004, Parallel and Distributed Computing and Networks.

[100]  Ran Ginosar,et al.  Data synchronization issues in GALS SoCs , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

[101]  Rainer Leupers,et al.  A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[102]  Tom Fitzpatric.  System Verilog for VHDL Users , 2004, DATE.

[103]  Ian O'Connor,et al.  Extremely Low-Power Logic , 2004, DATE '04.

[104]  Kees G. W. Goossens,et al.  Cost-performance trade-offs in networks on chip: a simulation-based approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[105]  Russell Tessier,et al.  An architecture and compiler for scalable on-chip communication , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[106]  Stephen B. Furber,et al.  An asynchronous on-chip network router with quality-of-service (QoS) support , 2004, IEEE International SOC Conference, 2004. Proceedings..

[107]  Jian Liu,et al.  Interconnect intellectual property for Network-on-Chip (NoC) , 2004, J. Syst. Archit..

[108]  Kees G. W. Goossens,et al.  An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[109]  Jörg Henkel,et al.  A case study in networks-on-chip design for embedded video , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[110]  Stephen P. Boyd,et al.  Managing power consumption in networks on chips , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[111]  D. Andreasson,et al.  On improving best-effort throughput by better utilization of guaranteed throughput channels in an on-chip communication system , 2004, Proceedings Norchip Conference, 2004..

[112]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[113]  Mahmut T. Kandemir,et al.  Fault tolerant algorithms for network-on-chip interconnect , 2004, IEEE Computer Society Annual Symposium on VLSI.

[114]  Jari Nurmi,et al.  Issues in the development of a practical NoC: the Proteo concept , 2004, Integr..

[115]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[116]  Simon W. Moore,et al.  Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[117]  Fernando Moraes,et al.  Evaluation of Routing Algorithms on Mesh Based NoCs , 2004 .

[118]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[119]  Luca Benini,et al.  Analyzing on-chip communication in a MPSoC environment , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[120]  Jens Sparsø,et al.  A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling , 2004, PATMOS.

[121]  Radu Marculescu,et al.  Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[122]  Jan Madsen,et al.  ARTS: a system-level framework for modeling MPSoC components and analysis of their causality , 2005, 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems.

[123]  Fabien Clermidy,et al.  An asynchronous NOC architecture providing low latency service and its multi-level design framework , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[124]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.

[125]  Giovanni De Micheli,et al.  Self-calibrating networks-on-chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[126]  Diederik Verkest,et al.  Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[127]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[128]  Kees G. W. Goossens,et al.  A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[129]  Hoi-Jun Yoo,et al.  An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[130]  Ran Ginosar,et al.  An asynchronous router for multiple service levels networks on chip , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[131]  Shashi Kumar,et al.  Slack-time aware routing in NoC systems , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[132]  Yusuf Leblebici,et al.  Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[133]  Ney Laert Vilar Calazans,et al.  MAIA - a framework for networks on chip generation and verification , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[134]  Donghyun Kim,et al.  A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[135]  Axel Jantsch,et al.  Power analysis of link level and end-to-end data protection in networks on chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[136]  Norbert Wehn,et al.  Network-on-chip-centric approach to interleaving in high throughput channel decoders , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[137]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[138]  Luca Benini,et al.  A novel approach for network on chip emulation , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[139]  Luciano Lavagno,et al.  Asynchronous on-chip networks , 2005 .

[140]  Jens Sparsø,et al.  Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[141]  Jörg Henkel,et al.  A methodology for design, modeling, and analysis of networks-on-chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[142]  Federico Angiolini,et al.  /spl times/pipes Lite: a synthesis oriented design library for networks on chips , 2005, Design, Automation and Test in Europe.

[143]  Jens Sparsø,et al.  A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip , 2005, Design, Automation and Test in Europe.

[144]  Wolf-Dietrich Weber,et al.  A quality-of-service mechanism for interconnection networks in system-on-chips , 2005, Design, Automation and Test in Europe.

[145]  Partha Pratim Pande,et al.  Effect of traffic localization on energy dissipation in NoC-based interconnect , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[146]  Jens Sparsø,et al.  An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip , 2005, 2005 International Symposium on System-on-Chip.

[147]  Jens Sparsø,et al.  The MANGO clockless network-on-chip: Concepts and implementation , 2006 .