A racetrack memory based in-memory booth multiplier for cryptography application
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[1] Chih-Wei Liu,et al. Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM) , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.
[2] G. Huang,et al. An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices , 2015, IEEE Transactions on Nanotechnology.
[3] Jacques-Olivier Klein,et al. Magnetic Adder Based on Racetrack Memory , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.
[4] Adi Shamir,et al. A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.
[5] Jeng-Shyang Pan,et al. Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b,2)-Way Karatsuba Decomposition , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[6] Rami G. Melhem,et al. Multilane Racetrack caches: Improving efficiency through compression and independent shifting , 2015, The 20th Asia and South Pacific Design Automation Conference.
[7] C. Rettner,et al. Current-Controlled Magnetic Domain-Wall Nanowire Shift Register , 2008, Science.
[8] Kaushik Roy,et al. TapeCache: a high density, energy efficient cache based on domain wall memory , 2012, ISLPED '12.
[9] H. Ohno,et al. Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions , 2008 .
[10] Yu Wang,et al. Hi-fi playback: Tolerating position errors in shift operations of racetrack memory , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).
[11] Amar Mandal,et al. Tripartite Modular Multiplication using Toom-Cook Multiplication , 2012 .
[12] Kailash Gopalakrishnan,et al. Overview of candidate device technologies for storage-class memory , 2008, IBM J. Res. Dev..
[13] Jian-Ping Wang,et al. A spintronics full adder for magnetic CPU , 2005 .
[14] S. Parkin,et al. Magnetic Domain-Wall Racetrack Memory , 2008, Science.
[15] Hai Li,et al. Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power , 2015, The 20th Asia and South Pacific Design Automation Conference.
[16] Yiran Chen,et al. Exploration of GPGPU register file architecture using domain-wall-shift-write based racetrack memory , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[17] Kaushik Roy,et al. STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[18] Hao Yu,et al. Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[19] Wenqing Wu,et al. Cross-layer racetrack memory design for ultra high density and low power consumption , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[20] Q. Stainer,et al. MRAM with soft reference layer: In-stack combination of memory and logic functions , 2013, 2013 5th IEEE International Memory Workshop.
[21] Alexander Albicki,et al. Low power and high speed multiplication design through mixed number representations , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.