A Study of FPGA Algorithm for consider the Power Consumption

In this paper, we proposed FPGA algorithm for consider the power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within FPGA. Separated the feasible cluster reduced power consumption using glitch removal method. Glitch removal appled delay buffer insertion method by signal process within the feasible cluster. Also, removal glitch between the feasible clusters by signal process for circuit. The experiments results show reduction in the power consumption by 7.14% comparing with that of [9].