On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling
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[1] Laurent Maillet-Contoz,et al. Using transactional level models in a SoC design flow , 2003 .
[2] Daniel Geist,et al. Combining system level modeling with assertion based verification , 2005, Sixth international symposium on quality electronic design (isqed'05).
[3] Stuart Swan,et al. A tutorial introduction on the new SystemC verification standard , 2003 .
[4] Mark Glasser,et al. The Transaction-Based Verification Methodology , 2000 .
[5] Imed Moussa,et al. An integrated design and verification methodology for reconfigurable multimedia systems , 2005, Design, Automation and Test in Europe.
[6] Thorsten Grotker,et al. System Design with SystemC , 2002 .
[7] Adam Donlin,et al. Transaction level modeling: flows and use models , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..
[8] Franco Fummi,et al. On the use of a high-level fault model to check properties incompleteness , 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..
[9] Orna Grumberg,et al. "Have I written enough Properties?" - A Method of Comparison between Specification and Implementation , 1999, CHARME.
[10] Frank Ghenassia,et al. Transaction Level Modeling with SystemC , 2005 .
[11] Daniel Gajski,et al. Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).